The present invention relates generally to the field of semiconductors and more specifically to the field of memory devices.
As half-pitches approach process nodes that are unsustainable by conventional lithography systems, techniques such as double exposure or double patterning have been used to extend the capabilities of conventional lithography equipment to shorter half-pitches. Double exposure, as its name implies, consists of exposing a single coating of resist twice, using two different masks. Features that are close together are exposed separately in order to counter the undesirable over-exposure which is a consequence of non-contact lithography methods.
Conventional memory array layout is rectangular. The memory cells of a memory array are laid out as a rectangular (Cartesian) grid. The standard rectangular layout is used because it is the logical way to structure an array and because conventional semiconductor processes are designed for a rectangular layout.
However, the half-pitch of a rectangular layout cannot be effectively reduced with double exposure techniques. For example, if the bit and word lines can be reduced by a factor of 2 using double exposure, the spacing of the layout of the memory cells can only be reduced by a factor of 1.4 using double exposure.